A nonvolatile memory device is widely used to be incorporated into portable hardware such as cellular phones and digital cameras and its use has spread at a high pace. In recent years, audio data and image data have been handled in many occasions and there have been strong demands for a nonvolatile memory device which has a larger capacity and is operative at a higher speed. Besides, in a field of the nonvolatile memory device for use with the portable hardware, a demand for lower electric power consumption has been increasing.
These days, a major nonvolatile memory device is a flash memory. The flash memory is configured to control electric charges accumulated on a floating gate to store data. It has been pointed out that since the flash memory has a structure for storing the electric charges on the floating gate in a high electric field, there is a limitation on reduction of its size and it is difficult to implement microfabrication required to achieve a larger capacity. In addition, the flash memory is required to erase specified blocks all at once for rewriting. Because of such characteristics, the flash memory requires a very long time for rewriting and has a limitation on achievement of a higher speed.
As a nonvolatile memory device in next generation which has a potential to solve these problems, there is a nonvolatile memory device including a resistance variable element configured to store data by changing its electric resistances. At present, MRAM (Magnetic RAM), PRAM (Phase-Change RAM), ReRAM (Resistive RAM), etc. have been proposed as nonvolatile memories using the resistance variable element.
Patent literature 1 discloses an exemplary control method of a bipolar ReRAM element including a perovskite structure oxide.
The bipolar ReRAM element refers to an element which changes to a high-resistance state in response to a voltage pulse with one of different polarities and changes to a low-resistance state in response to a voltage pulse with an opposite polarity. The ReRAM element refers to an element which is changeable reversibly at least between a first resistance state (high-resistance state, RH state or RH in a simple expression) and a second resistance state (low-resistance state, RL state or RL in a simple expression) in which a resistance value of the ReRAM element is lower than a resistance value of the ReRAM element in the first resistance state by application of electric stresses, and a nonvolatile memory configured to store data according to resistance values.
Hereinafter, the control method of the ReRAM element will be described with reference to the drawings.
FIGS. 36 to 38 show a control method of a memory cell disclosed in Patent literature 1. A memory cell 9 includes a resistance variable element 1 and a select transistor 2. One of two terminals of the resistance variable element 1 is electrically connected to one of two main terminals (drain or source) of the select transistor 2. The other main terminal (source or drain) of the select transistor 2 is electrically connected to a source line terminal 3 via a source line 6. The other terminal of the resistance variable element 1 is electrically connected to a bit line terminal 5 via a bit line 8. A gate of the select transistor 2 is electrically connected to a word line terminal 4 via a word line 7. In any of a case where data is written (when “1” is written, data “1” is allocated to RH (high-resistance state) of the ReRAM element), a case where data is erased (when “0” is written, data “0” is allocated to RL (low-resistance state) of the ReRAM element), and a case where data is read, a high-level threshold voltage (voltage for placing the transistor in an electrically conductive state) is applied to a word line terminal 4 of a selected memory cell, causing the select transistor 2 to be placed in an electrically conductive state.
FIG. 36 is a view showing an application state of a voltage pulse in a case where a write operation is performed in the memory cell of Patent literature 1. The source line 6 is set to 0 V (electrically grounded), a write pulse with a positive polarity and a predetermined write voltage amplitude is applied to the bit line 8, and desired data is written to the resistance variable element 1. When multi-valued data is written to the resistance variable element 1, the voltage amplitude of the write pulse is set to a level according to a value of data to be written. For example, in a case where four-valued data is written to one resistance variable element 1, one voltage amplitude is selected from among predetermined four voltage amplitudes determined according to respective values of write data and a write operation is performed. As the write pulse width, a proper width according to the element is selected. In other words, to change the resistance variable element 1 to a specified resistance state, there are one voltage amplitude level and one pulse width corresponding to the resistance state.
FIG. 37 is a view showing an application state of a voltage pulse in a case where an erase operation is performed in the memory cell of Patent literature 1. The bit line is set to 0V (electrically grounded), and an erase pulse with a positive polarity and a predetermined erase voltage amplitude is applied to the source line. By application of the erase pulse, the resistance variable element 1 is caused to have an electric resistance of a minimum value. Patent literature 1 discloses that by application of the erase pulse to a specified source line in a state where a plurality of bit lines are set to 0V, a plurality of memory cells connected to the plurality of bit lines and to the source line are erased all at once.
FIG. 38 is a view showing an application state of a voltage pulse in a case where a read operation is performed in the memory cell of Patent literature 1. When data stored in the resistance variable element 1 is read, the source line 6 is set to 0V (electrically grounded), a predetermined read voltage is applied to a selected bit line 8 by way of a read circuit. Upon application of the read voltage, a comparator and determiner circuit compares a level of the bit line 8 to a reference level for reading, and the stored data is read.
Patent literature 2 discloses a ReRAM configured to perform a unipolar operation in which the element is changeable to RH (high-resistance state) in response to a voltage Vb with one polarity and to RL (low-resistance state) in response to a voltage Va with the same polarity. It is recited that in particular, the unipolar ReRAM having a symmetric characteristic at positive and negative sides may be bipolar-drivable such that the element changes to the RL (low-resistance state) using Va with one polarity and changes to the RH (high-resistance state) using Vb with an opposite polarity. It is proposed that to change the resistance of the resistance variable element, a load resistor is connected in series with the resistance variable element, a resistance changing operation of the resistance variable element is stabilized by making a load resistance characteristic different between a case where the resistance variable element changes from RH to RL and a case where the resistance variable element changes from RL to RH as shown in FIG. 39. It is recited that, as conditions which are to be met by the respective load resistance characteristics, a resistance of a voltage-current characteristic of a load resistor (including a non-linear load such as a transistor) is set higher in the case where the element changes from RH to RL than in the case where the element changes from RL to RH, as shown in FIG. 39(A). Thereby, a current and a voltage at point T4 to which a current and a voltage at point Tb change are automatically lower than those at point Ta, and a current and a voltage at point T3 to which the current and the voltage at point Ta change are automatically lower than those at point Tb. Thus, a stable operation is implemented.
It should be noted that, to allow the unipolar ReRAM to be bipolar-drivable as described above, VB must be lower than VA in absolute value. On the other hand, a problem will not arise in an operation of a complete bipolar ReRAM, even if VB is higher than VA. Nonetheless, the bipolar ReRAM is favorably driven using the relation shown in FIG. 39, because it is necessary to change the element to RH with a current drivability for flowing a current more in amount than a current flowing just after the element has changed to RL.